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AMD Instinct™

Propelling improved & innovative ideas

Delivering Performance Leadership for the Data Center

AMD Instinct™ accelerators are engineered from the ground up for this new era of data center computing, supercharging HPC and AI workloads to propel new discoveries. The AMD Instinct™ family of accelerators can deliver industry leading performance for the data center at any scale from single server solutions up to the world’s largest supercomputers.1 With new innovations in AMD CDNA™ 2 architecture, AMD Infinity Fabric™ technology and packaging technology, the latest AMD Instinct™ accelerators are designed to power discoveries at exascale, enabling scientists to tackle our most pressing challenges.

Accelerate HPC Science & Research

For HPC workloads, the AMD Instinct™ MI250X delivers a dramatic 4X advantage to competitive GPUs with up to 47.9 TFLOPs double precision (FP64), and with new FP64 Matrix Core technology, up to 95.7 TFLOPs double precision (FP64 Matrix) peak theoretical performance.

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Faster Time to Learning & Insights

When it comes to delivering performance for machine and deep learning, the MI250X provides up to 383 TFLOPS peak theoretical half-precision (FP16) with up to 1.6x more memory capacity and bandwidth than competitive GPUs for the most demanding AI workloads.

(The TF32 data format is not IEEE compliant and not included in this comparison.)

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Maximize Throughput & Efficiency with First Multi-Die GPU

AMD Instinct™ accelerators are the industry's first accelerators engineered as a multi-chip GPU package with a state-of-the-art fabric designed with 3rd Gen AMD Infinity Fabric technology to enable a massive data throughput intelligently at ultra-high speeds for HPC and AI.

AMD Instinct™ accelerators are pushing the boundaries of computing by unifying the CPU and the GPU accelerator. 3rd Gen AMD Infinity Fabric technology adds direct CPU to GPU connectivity and enables cache coherency when deploying the MI250X accelerator and optimized 3rd Gen AMD EPYC CPUs, allowing a quick and simple on-ramp for CPU codes to tap the power of accelerators.

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